Digital Voice Systems VC-20-ATC-10B Spécifications Page 13
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Noté. / 5. Basé sur avis des utilisateurs
FAA20 Embedded NEXCOM Vocoder
Board Manual
This manual has been prepared for the Federal Aviation Administration.
FA100-00107 (March 2004) – Rev 1.0.0 Page 7
SIGNAL PIN DIR DESCRIPTION
DR B11 I Serial Receive Data: Linear 16-bit PCM voice is input to
the FAA20 at a rate of 8000 samples/second. Each
sample is received serially (MSB first) beginning with the
falling edge of the SCLK after the FSR signal is detected.
SCLK B9 I/O Serial Shift Clock: The serial shift clock transfers transmit
and receive serial data. Transmit data is output on the
rising edge of clock. Receive data is sampled on the
falling edge of clock.
FSX B7 I/O Serial Transmit Frame Sync (active high): The FAA20
samples this signal on the falling edge of SCLK. An
active signal begins the transfer of Transmit Data. The
FSX signal should be asserted for only one bit period at a
rate of 8 kHz.
FSR B12 I/O Serial Receive Frame Sync (active high): The FAA20
samples this signal on the falling edge of SCLK. An
active signal begins the transfer of Receive Data. The
FSR signal should be asserted for only one bit period at a
rate of 8 kHz.
SPRDY C7 O Serial Port Ready Status: Unlike the VC-20, the FAA20
serial port is dedicated to serial port transfers and is
always ready. This signal is tied to +5V with a pull up
resistor to insure compatibility with VC-20
implementations.
CONTROL/STATUS SIGNALS
RUN A6 O Run Status (active high): The FAA20 asserts this signal
when it actively encoding or decoding voice. The signal
is synchronous with ECLK. The FAA20 also lights LED6
when encoding or decoding; however, the LED6 state
changes are driven by the FAA20 DSP and are not
synchronous with ECLK.
Note: This bit is not functional in TEST mode.
RESX A7 O Reset Status (active low): The FAA20 asserts this signal
when reset is active. The signal is driven by the FAA20
hardware signal state and not driven by the FAA20 DSP
software. The FAA20 is reset under any of the following
conditions: power up, RSTI assertion, and/or FAA20
watchdog timeout.
DINRS A15 I Reset Signal (active high): The reset signal can be
externally asserted to reset the FAA20. An active signal
with a minimum duration of 300 ns resets the board. A
built-in pull-up resister disables this signal when the pin is
left unconnected.
ECHO A23 I
rsvd
Echo Canceller Enable (active low): The FAA20 does not
include a built-in echo canceller. The FAA20 software
ignores this signal. A built-in pull-up resister disables this
signal when the pin is left unconnected.
VAD A22 I Voice Detection Enable (active low): This signal must be
asserted to enable FAA20 voice/silence detection and
comfort noise generation. This signal is sampled on the
falling edge of DCLK. A built-in pull-up resister disables
this signal when the pin is left unconnected.
Note: This bit is not functional in TEST mode.
DDET A17 O
rsvd
DTMF Detection Status (active high): This signal is not
used by the FAA20. During power up, it is initialized to
the low (inactive) state.
- FA100-00107 1
- BOARD MANUAL 1
- Board Manual 2
- 1.0 INTRODUCTION 7
- 2.0 GENERAL DESCRIPTION 9
- 2.2 Features 10
- 3.1 Main Signal Connector 11
- Table 1: DIN Signals 12
- 3.2 Terminal Connectors 15
- 3.3 Audio Connectors 16
- 3.4 LED Indicators 17
- 3.5 Switch Controls 18
- 4.0 INSTALLATION 19
- 4.3.1 Timing Configuration 20
- 5.0 FUNCTIONAL DESCRIPTION 23
- 5.1.3 DEMO Mode 24
- 5.2 Interfaces 25
- 5.2.3 NIB Interface 26
- 5.3 Voice Processing 28
- PACKET VOICE ROUTER 31
- 5.4.1 Truncated Timing Mode 34
- 5.4.2 Voice Delay 35
- 5.4.3 Programmable LEDs 37
- 5.4.4 Command Processor 39
- 6.1 Hardware Architecture 40
- 6.1.2 Memory Maps 42
- Figure 17: Data Memory Map 43
- Figure 19: Flash Memory Map 44
- 6.2 Software Architecture 45
- Table 8: Thread List 47
- 7.0 MAINTENANCE AND TEST 50
- 7.2.1 Audio Tools 52
- 7.2.2 Nibble Tools 54
- 7.2.3 PCM Tools 54
- 7.3.1 Standard Mode Upgrade 55
- 7.4.1 Test Vector Execution 59
- 7.4.2 DAT2LIN Utility 61
- 7.4.3 BIT2CMP Utility 62
- 8.1 Command Overview 63
- 8.2 Built-In Help 65
- 8.3 Command Reference 66
- 8.3.1 ADAPT 67
- 8.3.2 BIT 68
- Latched 70
- 8.3.3 CFG 71
- 8.3.4 CLKDET 73
- 8.3.5 CLKRATE 74
- 8.3.6 CLKREF 76
- 8.3.7 CLKSRC 77
- 8.3.8 COMCFG 78
- 8.3.9 COMECHO 79
- 8.3.10 COMPROMPT 80
- 8.3.11 COUNT 81
- 8.3.12 DELAY 83
- 8.3.13 DM 84
- 8.3.14 DUMP 85
- 8.3.15 FLASH 86
- 8.3.16 FM 87
- 8.3.17 FRAMESIZE 88
- 8.3.18 GAM 89
- 8.3.19 IO 90
- 8.3.20 LED 91
- 8.3.21 LOOP 92
- 8.3.22 MACRO 93
- 8.3.23 MCBSP 94
- 8.3.24 MIX 95
- 8.3.25 OPMODE 96
- 8.3.26 PROG 97
- 8.3.27 REM 98
- 8.3.28 RESET 99
- 8.3.29 ROUTE 100
- 8.3.30 TEST 101
- 8.3.31 TONE 103
- 8.3.32 TRUN 104
- 8.3.33 VERSION 105
- 8.3.34 VOC 106
- 8.3.35 WAIT 108
- 9.0 GLOSSARY 109
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